a
FEATURES3 V/5 V Power Supply25 MHz SpeedOn-Chip SINE Look-Up TableOn-Chip 10-Bit DACParallel LoadingPowerdown Option72 dB SFDR125 mW (5 V) Power Consumption40 mW (3 V) Power Consumption48-Pin TQFPAPPLICATIONSDDS TuningDigital DemodulationGENERAL DESCRIPTIONCMOSComplete DDSAD9831This DDS device is a numerically controlled oscillator employ-ing a phase accumulator, a sine look-up table and a 10-bit D/Aconverter integrated on a single CMOS chip. Modulationcapabilities are provided for phase modulation and frequencymodulation.Clock rates up to 25 MHz are supported. Frequency accuracycan be controlled to one part in 4 billion. Modulation is effectedby loading registers through the parallel microprocessorinterface.A powerdown pin allows external control of a powerdownmode. The part is available in a 48-pin TQFP package.FUNCTIONAL BLOCK DIAGRAMDVDDMCLKFSELECTFREQ0 REGMUXFREQ1 REGPHASEACCUMULATOR(32-BIT)DGNDAVDDAGNDREFOUTFS ADJUSTREFINON-BOARDREFERENCEFULL-SCALECONTROLCOMPΣ12SINROM10-BIT DACIOUTPHASE0 REGPHASE1 REGPHASE2 REGPHASE3 REGMUXAD9831PARALLEL REGISTERTRANSFER CONTROLSLEEPRESETMPU INTERFACED0D15WRA0A1A2PSEL0PSEL1REV.A
Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 617/329-4700Fax: 617/326-8703
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AD9831–SPECIFICATIONSParameterSIGNAL DAC SPECIFICATIONSResolutionUpdate Rate (fMAX)IOUT Full ScaleOutput ComplianceDC AccuracyIntegral NonlinearityDifferential NonlinearityDDS SPECIFICATIONS2Dynamic SpecificationsSignal to Noise RatioTotal Harmonic DistortionSpurious Free Dynamic Range (SFDR)3Narrow Band (±50 kHz)Wide Band (±2 MHz)Clock FeedthroughWake-Up Time4Powerdown OptionVOLTAGE REFERENCEInternal Reference @ +25°CTMIN to TMAXREFIN Input ImpedanceReference TCREFOUT Output ImpedanceLOGIC INPUTSVINH, Input High VoltageVINL, Input Low VoltageIINH, Input CurrentCIN, Input CapacitancePOWER SUPPLIESAVDDDVDDIAAIDDIAA + IDD5Low Power Sleep Mode61025451.5±1±0.51(VDD = +3.3 V ؎ 10%; +5 V ؎ 10%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN =
REFOUT; RSET = 3.9 k⍀; RLOAD = 300 ⍀ for IOUT unless otherwise noted)
UnitsBitsMSPS nommA nommA maxV maxLSB typLSB typTest Conditions/CommentsAD9831A50–53–72–70–50–601Yes1.211.21 ± 7%10100300VDD – 0.90.910102.97/5.52.97/5.5122.5 + 0.33/MHz15241dB mindBc maxdBc mindBc mindBc mindBc typms typfMCLK = 25 MHz, fOUT = 1 MHzfMCLK = 25 MHz, fOUT = 1 MHzfMCLK = 6.25 MHz, fOUT = 2.11 MHz5 V Power Supply3 V Power SupplyVolts typVolts min/maxMΩ typppm/°C typΩ typV minV maxµA maxpF maxV min/V maxV min/V maxmA maxmA typmA maxmA maxmA max5 V Power Supply5 V Power Supply3 V Power Supply5 V Power Supply1 MΩ Resistor Tied Between REFOUT and AGNDNOTES1Operating temperature range is as follows: A Version: –40°C to +85°C.2100% production tested.3fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.4See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.5Measured with the digital inputs static and equal to 0 V or DVDD.6The Low Power Sleep Mode current is typically 2 mA when a 1 MΩ resistor is not tied between REFOUT and AGND.The AD9831 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenu-ated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.Specifications subject to change without notice.RSET3.9kΩ10nFREFOUTREFINFSADJUSTCOMPAVDD10nFON-BOARDREFERENCEFULL-SCALECONTROL12SINROM10-BIT DACIOUT300Ω50pFAD9831Figure 1.Test Circuit with Which Specifications Are Tested–2–REV. A
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AD9831
TIMING CHARACTERISTICSParametert1t2t3t4*t4A*t5t6t7t8t9*t9A*t10Limit atTMIN to TMAX(A Version)401616888t15388t1(VDD = +3.3 V ؎ 10%, +5 V ؎ 10%; AGND = DGND = 0 V, unless otherwise noted)
Unitsns minns minns minns minns minns minns minns minns minns minns minns minTest Conditions/CommentsMCLK PeriodMCLK High DurationMCLK Low DurationWR Rising Edge to MCLK Rising EdgeWR Rising Edge After MCLK Rising EdgeWR Pulse WidthDuration between Consecutive WR PulsesData/Address Setup TimeData/Address Hold TimeFSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising EdgeFSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising EdgeRESET Pulse Duration*See Pin Description section.Guaranteed by design but not production tested. t1MCLK t2 t4AWR t3 t5t4 t6Figure 2.Clock Synchronization Timing t6 t5WRt8 t7A0, A1, A2DATAVALID DATAVALID DATAFigure 3.Parallel TimingMCLKt9FSELECTPSEL0, PSEL1VALID DATAVALID DATAt9AVALID DATA t10RESETFigure 4.Control TimingREV. A
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AD9831
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 VDVDD to DGND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 VAVDD to DVDD . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 VAGND to DGND. . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 VDigital I/O Voltage to DGND . . . . .–0.3 V to DVDD + 0.3 VAnalog I/O Voltage to AGND . . . . .–0.3 V to AVDD + 0.3 VOperating Temperature RangeIndustrial (A Version) . . . . . . . . . . . . . . . .–40°C to +85°CStorage Temperature Range . . . . . . . . . . . .–65°C to +150°CMaximum Junction Temperature . . . . . . . . . . . . . . . .+150°CTQFP θJA Thermal Impedance . . . . . . . . . . . . . . . . .75°C/WLead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°CESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V*Stresses above those listed under “Absolute Maximum Ratings” may causepermanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions above those listed in theoperational sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.ORDERING GUIDETemperaturePackagePackageModelRangeDescriptionOption*AD9831AST–40°C to +85°C48-Pin TQFPST-48EVAL-AD9831EBEvaluation Board*ST = Thin Quad Flatpack (TQFP).–4–
PIN CONFIGURATIONTSUDDPNJNDDDMDIATDVGCCVOF UDCCAANNAECRSFOVNIAN484746454443424140393837AGND136AGNDREFOUT2PIN 1IDENTIFIER35RESETSLEEP334A0DVDD433A1DVDD532DGND6AD9831A231DB0MCLK7TOP VIEWWR8(Not to Scale)30DB129DGNDDVDD928DB2FSELECT1027DB3PSEL01126DB4PSEL11225DVDD131415161718192021222324D5431098765N1GB112BB1B11BBBBBBBDDDDDDDDDDDDNC = NO CONNECTREV. A
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AD9831
PIN DESCRIPTIONMnemonicFunctionPOWER SUPPLYAVDDPositive power supply for the analog section. A 0.1 µF decoupling capacitor should be connected between AVDDand AGND. AVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.AGNDAnalog Ground.DVDDPositive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDDand DGND. DVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.DGNDDigital Ground.ANALOG SIGNAL AND REFERENCEIOUTCurrent Output. This is a high impedance current source. A load resistor should be connected between IOUTand AGND.FS ADJUSTFull-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines themagnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows:IOUTFULL-SCALE = 12.5 × VREFIN/RSET VREFIN = 1.21 V nominal, RSET = 3.9 kΩ typicalREFINVoltage Reference Input. The AD9831 can be used with either the on-board reference, which is available from pinREFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9831accepts a reference of 1.21 V nominal.REFOUTVoltage Reference Output. The AD9831 has an on-board reference of value 1.21 V nominal. The reference ismade available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUTto REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.COMPCompensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramiccapacitor should be connected between COMP and AVDD.DIGITAL INTERFACE AND CONTROLMCLKDigital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. Theoutput frequency accuracy and phase noise are determined by this clock.FSELECTFrequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phaseaccumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when anMCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of oneMCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a changeon FSELECT should not coincide with an MCLK rising edge.WRWrite, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9831. The data is loadedinto the AD9831 on the rising edge of the WR pulse. This data is then loaded into the destination register on theMCLK rising edge. The WR pulse rising edge should not coincide with the MCLK rising edge as there will be anuncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The WR risingedge should occur before an MCLK rising edge. The data will then be loaded into the destination register on theMCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the destinationregister will be loaded on the next MCLK rising edge.D0–D15Data Bus, Digital Inputs for destination registers.A0–A2Address Digital Inputs. These address bits are used to select the destination register to which the digital data is tobe written.PSEL0, PSEL1Phase Select Input. The AD9831 has four phase registers. These registers can be used to alter the value beinginput to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, theinputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK risingedge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phaseregister.SLEEPLow Power Control, active low digital input. SLEEP puts the AD9831 into a low power mode. Internal clocksare disabled and the DAC’s current sources and REFOUT are turned off. The AD9831 is re-enabled by takingSLEEP high.RESETReset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analogoutput of midscale.REV. A
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AD9831
TERMINOLOGYIntegral NonlinearityThis is the maximum deviation of any code from a straight linepassing through the endpoints of the transfer function. Theendpoints of the transfer function are zero scale, a point 0.5LSB below the first code transition (000...00 to 000...01)and full scale, a point 0.5 LSB above the last code transition(111...10 to 111...11). The error is expressed in LSBs.Differential Nonlinearity±2 MHz about the fundamental frequency. The narrow bandSFDR gives the attenuation of the largest spur or harmonic in abandwidth of ±50 kHz about the fundamental frequency.Clock FeedthroughThere will be feedthrough from the MCLK input to the analogoutput. Clock feedthrough refers to the magnitude of theMCLK signal relative to the fundamental frequency in theAD9831’s output spectrum.Table I.Control RegistersThis is the difference between the measured and ideal 1 LSBchange between two adjacent codes in the DAC.Signal to (Noise + Distortion)RegisterFREQ0 REGSize32 BitsDescriptionFrequency Register 0. This de-fines the output frequency, whenFSELECT = 0, as a fraction of theMCLK frequency.Frequency Register 1. This de-fines the output frequency, whenFSELECT = 1, as a fraction of theMCLK frequency.Phase Offset Register 0. WhenPSEL0 = PSEL1 = 0, the contentsof this register are added to theoutput of the phase accumulator.Phase Offset Register 1. WhenPSEL0 = 1 and PSEL1 = 0, the con-tents of this register are added tothe output of the phase accumulator.Phase Offset Register 2. WhenPSEL0 = 0 and PSEL1 = 1, the con-tents of this register are added tothe output of the phase accumulator.Phase Offset Register 3. WhenPSEL0 = PSEL1 = 1, the contentsof this register are added to theoutput of the phase accumulator.Signal to (Noise + Distortion) is measured signal to noise at theoutput of the DAC. The signal is the rms magnitude of thefundamental. Noise is the rms sum of all the nonfundamentalsignals up to half the sampling frequency (fMCLK/2) but exclud-ing the dc component. Signal to (Noise + Distortion) isdependent on the number of quantization levels used in thedigitization process; the more levels, the smaller the quantiza-tion noise. The theoretical Signal to (Noise + Distortion) ratiofor a sine wave input is given bySignal to (Noise + Distortion) = (6.02N + 1.76) dBwhere N is the number of bits. Thus, for an ideal 10-bit con-verter, Signal to (Noise + Distortion) = 61.96 dB.Total Harmonic DistortionFREQ1 REG32 BitsPHASE0 REG12 BitsPHASE1 REG12 BitsTotal Harmonic Distortion (THD) is the ratio of the rms sumof harmonics to the rms value of the fundamental. For theAD9831, THD is defined as(V2+V3+V4+V5+V6THD=20logV1 22222PHASE2 REG12 Bitswhere V1 is the rms amplitude of the fundamental and V2, V3,V4, V5 and V6 are the rms amplitudes of the second through thesixth harmonic.Output CompliancePHASE3 REG12 BitsThe output compliance refers to the maximum voltage whichcan be generated at the output of the DAC to meet the specifi-cations. When voltages greater than that specified for theoutput compliance are generated, the AD9831 may not meetthe specifications listed in the data sheet.Spurious Free Dynamic RangeTable II.Addressing the Control RegistersA200001111A100110011A001010101Destination RegisterFREQ0 REG 16 LSBsFREQ0 REG 16 MSBsFREQ1 REG 16 LSBsFREQ1 REG 16 MSBsPHASE0 REGPHASE1 REGPHASE2 REGPHASE3 REGAlong with the frequency of interest, harmonics of the funda-mental frequency and images of the MCLK frequency arepresent at the output of a DDS device. The spurious free dy-namic range (SFDR) refers to the largest spur or harmonicwhich is present in the band of interest. The wide band SFDRgives the magnitude of the largest harmonic or spur relative tothe magnitude of the fundamental frequency in the bandwidthTable III.Frequency Register BitsD15MSBD0LSBTable IV.Phase Register BitsD15XD14XD13XD12XD11MSBD0LSB–6–
REV. A
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Typical Performance Characteristics–AD9831
25
TA = +25°C20Am+5V – TN15
ERRUC L10
ATOT+3.3V5
0
510152025MCLK FREQUENCY – MHz
Figure 5.Typical Current Consumption vs. MCLKFrequency–50 fOUT/fMCLK = 1/3 AVDD = DVDD = +3.3V–55Bd–60 – )zHk05–65±( RDFS–70–75–8010152025MCLK FREQUENCY – MHzFigure 6.Narrow Band SFDR vs. MCLK Frequency–40
fOUT/fMCLK = 1/3AVDD = DVDD = +3.3V–45
Bd – )–50
zHM2±( R–55
DFS–60
–65
10152025MCLK FREQUENCY – MHz
Figure 7.Wide Band SFDR vs. MCLK Frequency–40
AVDD = DVDD = +3.3V–45
–50
B25MHzd ––55 )zH10MHzM2–60±( RD–65FS–70–75
–80
00.10.20.30.4fOUT/fMCLK
Figure 8.Wide Band SFDR vs. fOUT/fMCLK for VariousMCLK Frequencies60AVDD = DVDD = +3.3VfOUT = fMCLK/355Bd – 50RNS454010152025MCLK FREQUENCY – MHzFigure 9.SNR vs. MCLK Frequency60AVDD = DVDD = +3.3V5510MHzBd – 50R25MHzNS454000.10.20.30.4fOUT/fMCLKFigure 10.SNR vs. fOUT/fMCLK for Various MCLKFrequencies–7–
REV. A
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AD9831–Typical Performance Characteristics
10
AVDD = DVDD = +2.97V7.5sm – EMIT P5.0
U-EKAW2.5
0–40–30–20–100TEMPERATURE – °C
Figure 11.Wake-Up Time vs. Temperature0–10–20–30V–40ID/Bd–5001–60–70–80–90–100START 0HzSTOP 12.5MHzRBW 300HzVBW 1kHzST 277 SECFigure 12.fMCLK = 25 MHz, fOUT = 1.1 MHz, FrequencyWord = B4395810–10–20–30V–40ID/Bd–5001–60–70–80–90–100START 0HzSTOP 12.5MHzRBW 300HzVBW 1kHzST 277 SECFigure 13.fMCLK = 25 MHz, fOUT = 2.1 MHz, FrequencyWord = 158106250–10–20
–30V–40ID/Bd–5001–60–70
–80–90
–100
START 0HzSTOP 12.5MHzRBW 300Hz
VBW 1kHz
ST 277 SEC
Figure 14.fMCLK = 25 MHz, fOUT = 3.1 MHz, FrequencyWord = 1FBE76C90–10–20–30V–40ID/Bd–5001–60–70–80–90–100
START 0HzSTOP 12.5MHzRBW 300Hz
VBW 1kHz
ST 277 SEC
Figure 15.fMCLK = 25 MHz, fOUT = 4.1 MHz, FrequencyWord = 29FBE76D0–10–20–30V–40ID/Bd–5001–60–70–80–90–100START 0HzSTOP 12.5MHzRBW 300HzVBW 1kHzST 277 SECFigure 16.fMCLK = 25 MHz, fOUT = 5.1 MHz, FrequencyWord = 34395810–8–
REV. A
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0–10–20–30V–40ID/Bd–5001–60–70–80–90–100
START 0HzSTOP 12.5MHzRBW 300Hz
VBW 1kHz
ST 277 SEC
Figure 17.fMCLK = 25 MHz, fOUT = 6.1 MHz, FrequencyWord = 3E76C8B40–10–20–30V–40ID/Bd–5001–60–70–80–90–100START 0HzSTOP 12.5MHzRBW 300HzVBW 1kHzST 277 SECFigure 18.fMCLK = 25 MHz, fOUT = 7.1 MHz, FrequencyWord = 48B43958REV. A
AD9831
0–10–20–30V–40ID/Bd–5001–60–70–80–90–100
START 0HzSTOP 12.5MHzRBW 300Hz
VBW 1kHz
ST 277 SEC
Figure 19.fMCLK = 25 MHz, fOUT = 8.1 MHz, FrequencyWord = 52F1A9FC0–10–20–30V–40ID/Bd–5001–60–70–80–90–100START 0HzSTOP 12.5MHzRBW 300HzVBW 1kHzST 277 SECFigure 20.fMCLK = 25 MHz, fOUT = 9.1 MHz, FrequencyWord = 5D2F1AA0–9–
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AD9831
CIRCUIT DESCRIPTIONThe AD9831 provides an exciting new level of integration forthe RF/Communications system designer. The AD9831 com-bines the Numerical Controlled Oscillator (NCO), SINE Look-Up Table, Frequency and Phase Modulators, and a Digital-to-Analog Converter on a single integrated circuit.The internal circuitry of the AD9831 consists of three mainsections. These are:Numerical Controlled Oscillator (NCO) + Phase ModulatorSINE Look-Up TableDigital-to-Analog ConverterThe AD9831 is a fully integrated Direct Digital Synthesis(DDS) chip. The chip requires one reference clock, one lowprecision resistor and eight decoupling capacitors to providedigitally created sine waves up to 12.5 MHz. In addition to thegeneration of this RF signal, the chip is fully capable of a broadrange of simple and complex modulation schemes. Thesemodulation schemes are fully implemented in the digital domainallowing accurate and simple realization of complex modulationalgorithms using DSP techniques.THEORY OF OPERATIONNumerical Controlled Oscillator + Phase ModulatorThis consists of two frequency select registers, a phase accumu-lator and four phase offset registers. The main component of theNCO is a 32-bit phase accumulator which assembles the phasecomponent of the output signal. Continuous time signals have aphase range of 0 to 2π. Outside this range of numbers, thesinusoid functions repeat themselves in a periodic manner. Thedigital implementation is no different. The accumulator simplyscales the range of phase numbers into a multibit digital word.The phase accumulator in the AD9831 is implemented with 32bits. Therefore, in the AD9831, 2π = 232. Likewise, the ∆Phaseterm is scaled into this range of numbers 0 < ∆Phase < 232 – 1.Making these substitutions into the equation abovef = ∆Phase × fMCLK/232where 0 < ∆Phase < 232With a clock signal of 25 MHz and a phase word of 051EB852hexf = 51EB852 × 25 MHz/232 = 0.500000000465 MHzThe input to the phase accumulator (i.e., the phase step) can beselected either from the FREQ0 Register or FREQ1 Registerand this is controlled by the FSELECT pin. NCOs inherentlygenerate continuous phase signals, thus avoiding any outputdiscontinuity when switching between frequencies.Following the NCO, a phase offset can be added to performphase modulation using the 12-bit PHASE Registers. The con-tents of this register are added to the most significant bits of theNCO. The AD9831 has four PHASE registers, the resolutionof these registers being 2π/4096.Sine Look-Up Table (LUT)Sine waves are typically thought of in terms of their magnitudeform a(t) = sin (ωt). However, these are nonlinear and not easyto generate except through piece wise construction. On theother hand, the angular information is linear in nature. That is,the phase angle rotates through a fixed angle for each unit oftime. The angular rate depends on the frequency of the signalby the traditional rate of ω = 2πf.MAGNITUDE+10–12πPHASETo make the output useful, the signal must be converted fromphase information into a sinusoidal value. Since phase informa-tion maps directly into amplitude, a ROM LUT converts thephase information into amplitude. To do this, the digital phaseinformation is used to address a sine ROM LUT. Although theNCO contains a 32-bit phase accumulator, the output of theNCO is truncated to 12 bits. Using the full resolution of thephase accumulator is impractical and unnecessary as this wouldrequire a look-up table of 232 entries.It is necessary only to have sufficient phase resolution in theLUTs such that the dc error of the output waveform is domi-nated by the quantization error in the DAC. This requires thelook-up table to have two more bits of phase resolution than the10-bit DAC.Digital-to-Analog Converter0Figure 21.Sine WaveKnowing that the phase of a sine wave is linear and given areference interval (clock period), the phase rotation for thatperiod can be determined.∆Phase = ωδtSolving for ωω = ∆Phase/δt = 2πfSolving for f and substituting the reference clock frequency forthe reference period (1/fMCLK = δt)f = ∆Phase × fMCLK/2πThe AD9831 builds the output based on this simple equation.A simple DDS chip can implement this equation with threemajor subcircuits.The AD9831 includes a high impedance current source 10-bitDAC, capable of driving a wide range of loads at differentspeeds. Full-scale output current can be adjusted, for optimumpower and external load requirements, through the use of asingle external resistor (RSET).The DAC is configured for single ended operation. The loadresistor can be any value required, as long as the full-scale volt-age developed across it does not exceed the voltage compliancerange. Since full-scale current is controlled by RSET, adjust-ments to RSET can balance changes made to the load resistor.However, if the DAC full-scale output current is significantlyless than 4 mA, the DAC’s linearity may degrade.–10–
REV. A
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AD9831
DSP and MPU InterfacingThe AD9831 has a parallel interface, with 16 bits of data beingloaded during each write cycle.The frequency or phase registers are loaded by asserting the WRsignal. The destination register for the 16 bit data is selectedusing the address inputs A0, A1 and A2. The phase registersare 12 bits wide so, only the 12 LSBs need to be valid—the4 MSBs of the 16 bit word do not have to contain valid data.Data is loaded into the AD9831 by pulsing WR low, the databeing latched into the AD9831 on the rising edge of WR. Thevalues of inputs A0, A1 and A2 are also latched into theAD9831 on the WR rising edge. The appropriate destinationregister is updated on the next MCLK rising edge. If the WRrising edge coincides with the MCLK rising edge, there is anuncertainty of one MCLK cycle regarding the loading of thedestination register—the destination register may be loadedimmediately or the destination register may be updated on thenext MCLK rising edge. To avoid any uncertainty, the timeslisted in the specifications should be complied with.FSELECT, PSEL0 and PSEL1 are sampled on the MCLKrising edge. Again, these inputs should be valid when anMCLK rising edge occurs as there will be an uncertainty of oneMCLK cycle introduced otherwise. When these inputs changevalue, there will be a pipeline delay before control is transferredto the selected register—there will be a pipeline delay before theanalog output is controlled by the selected register. There is asimilar delay when a new word is written to a register. PSEL0,PSEL1, FSELECT and WR have latencies of six MCLK cycles.The flow chart in Figure 22 shows the operating routine for theAD9831. When the AD9831 is powered up, the part should bereset using RESET. This will reset the phase accumulator tozero so that the analog output is at midscale. RESET does notreset the phase and frequency registers. These registers willcontain invalid data and, therefore, should be set to zero by theuser.The registers to be used should be loaded, the analog outputbeing fMCLK/232 × FREG where FREG is the value loaded intothe selected frequency register. This signal will be phase shiftedby the amount specified in the selected phase register (2π/4096× PHASEREG where PHASEREG is the value contained in theselected phase register). When FSELECT, PSEL0 and PSEL1are programmed, there will be a pipeline delay of approximately6 MCLK cycles before the analog output reacts to the changeon these inputs.RESETDATA WRITEFREG<0, 1> = 0PHASEREG<0, 1, 2, 3> = 0DATA WRITEFREG<0> = fOUT0/fMCLK*232FREG<1> = fOUT1/fMCLK*232PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>SELECT DATA SOURCESSET FSELECTSET PSEL0, PSEL1WAIT 6 MCLK CYCLESDAC OUTPUTVOUT = VREFIN*6.25*ROUT/RSET*(1 + SIN(2π(FREG*fMCLK*t/232 + PHASEREG/212)))CHANGE PHASE?NONOCHANGE FOUT?YESCHANGE FREG?YESYESNOCHANGE FSELECTCHANGE PHASEREG?YESNOCHANGE PSEL0, PSEL1Figure 22. Flow Chart for AD9831 Initialization and OperationREV. A
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AD9831
APPLICATIONSThe AD9831 contains functions which make it suitable formodulation applications. The part can be used to performsimple modulation such as FSK. More complex modulationschemes such as GMSK and QPSK can also be implementedusing the AD9831. In an FSK application, the two frequencyregisters of the AD9831 are loaded with different values; onefrequency will represent the space frequency while the other willrepresent the mark frequency. The digital data stream is fed tothe FSELECT pin which will cause the AD9831 to modulatethe carrier frequency between the two values.The AD9831 has four phase registers; this enables the part toperform PSK. With phase shift keying, the carrier frequency isphase shifted, the phase being altered by an amount which isrelated to the bit stream being input to the modulator. Thepresence of four shift registers eases the interaction neededbetween the DSP and the AD9831.The frequency and phase registers can be written to continu-ously, if required. The maximum update rate equals thefrequency of the MCLK. However, if a selected register isloaded with a new word, there will be a delay of 6 MCLK cyclesbefore the analog output will change accordingly.The AD9831 is also suitable for signal generator applications.With its low current consumption, the part is suitable for appli-cations in which it can be used as a local oscillator. In addition,the part is fully specified for operation with a +3.3 V ± 10%power supply. Therefore, in portable applications where currentconsumption is an important issue, the AD9831 is perfect.Grounding and Layoutdevice requiring an AGND to DGND connection, then theground planes should be connected at the AGND and DGNDpins of the AD9831. If the AD9831 is in a system where mul-tiple devices require AGND to DGND connections, theconnection should be made at one point only, a star groundpoint that should be established as close as possible to theAD9831.Avoid running digital lines under the device as these will couplenoise onto the die. The analog ground plane should be allowedto run under the AD9831 to avoid noise coupling. The powersupply lines to the AD9831 should use as large a track as ispossible to provide low impedance paths and reduce the effectsof glitches on the power supply line. Fast switching signals suchas clocks should be shielded with digital ground to avoid radiat-ing noise to other sections of the board. Avoid crossover ofdigital and analog signals. Traces on opposite sides of the boardshould run at right angles to each other. This will reduce theeffects of feedthrough through the board. A microstrip tech-nique is by far the best but is not always possible with adouble-sided board. In this technique, the component side ofthe board is dedicated to ground planes while signals are placedon the other side.Good decoupling is important. The analog and digital suppliesto the AD9831 are independent and separately pinned out tominimize coupling between analog and digital sections of thedevice. All analog and digital supplies should be decoupled toAGND and DGND respectively with 0.1 µF ceramic capacitorsin parallel with 10 µF tantalum capacitors. To achieve the bestfrom the decoupling capacitors, they should be placed as closeas possible to the device, ideally right up against the device. Insystems where a common supply is used to drive both theAVDD and DVDD of the AD9831, it is recommended that thesystem’s AVDD supply be used. This supply should have therecommended analog supply decoupling between the AVDDpins of the AD9831 and AGND and the recommended digitalsupply decoupling capacitors between the DVDD pins andDGND.The printed circuit board that houses the AD9831 should bedesigned so that the analog and digital sections are separatedand confined to certain areas of the board. This facilitates theuse of ground planes which can be separated easily. A mini-mum etch technique is generally best for ground planes as itgives the best shielding. Digital and analog ground planesshould only be joined in one place. If the AD9831 is the only–12–
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AD9831
AD9831 Evaluation BoardUsing the AD9831 Evaluation BoardThe AD9831 Evaluation Board allows designers to evaluate thehigh performance AD9831 DDS Modulator with a minimum ofeffort.To prove that this device will meet the user’s waveform synthe-sis requirements, the user only requires a 3.3 V or 5 V powersupply, an IBM-compatible PC and a spectrum analyzer alongwith the evaluation board. The evaluation setup is shownbelow.The DDS Evaluation kit includes a populated, tested AD9831printed circuit board along with the software which controls theAD9831 in a Windows environment.IBM COMPATIBLE PCPARALLEL PORTCENTRONICSPRINTER CABLEAD9831.EXEThe AD9831 Evaluation kit is a test system designed to simplifythe evaluation of the AD9831. Provisions to control theAD9831 from the printer port of an IBM-compatible PC areincluded along with the necessary software. An application noteis also available with the evaluation board which gives informa-tion on operating the evaluation board.Prototyping AreaAn area is available on the evaluation board where the user canadd additional circuits to the evaluation test set. Users maywant to build custom analog filters for the output or add buffersand operational amplifiers which are to be used in the finalapplication.XO vs. External ClockAD9831EVALUATIONBOARDThe AD9831 can operate with master clocks up to 25 MHz. A25 MHz oscillator is included on the evaluation board. How-ever, this oscillator can be removed and an external CMOSclock connected to the part, if required.Power SupplyFigure 23.AD9831 Evaluation Board SetupPower to the AD9831 Evaluation Board must be provided ex-ternally through the pin connections. The power leads shouldbe twisted to reduce ground loops.REV. A
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AD9831
DVDDC1, C2, C30.1µF123456789101112131415161718192021222324252627282930313233343536DVDDLATCHD0D1D2D3D4D5D6D7C140.1µFVDDDVDD4, 5, 9, 25D15D15D842C710nFAVDD38, 43, 47AVDDAVDDC4, C5, C60.1µF1421J1PCINTERFACEWRRESETLATCHLOADD7DVDDC150.1µF74HC574CKLOADU2COMPVDD74HC574CK2231U3D7D0REFIN41LK5REFINAD9831U4REFOUT2RESETD0LATCH3234WR83512C810nFA2A0WRRESETPSEL1C1010µFDVDDJ2C90.1µFJ3C110.1µFAVDDC1210µFR110kΩPSEL1R210kΩR310kΩLK1RESETPSEL0LK2LOADFSELECTLK3MCLKDVDDLK411PSEL0FSADJUST40R53.9kΩIOUTR6300Ω107FSELECTMCLKIOUT39WRSWDVDD3SLEEPDGND6, 13, 29AGND1, 36, 46MCLKR450ΩDVDDC130.1µFDVDDU1OUTXTAL1DGNDFigure 24. AD9831 Evaluation Board LayoutCOMPONENT LISTIntegrated CircuitsXTAL1U2, U3U4CapacitorsC1–C6C7, C8C9, C11, C13–C15C10, C12ResistorsR1–R3R4R5R6OSC XTAL 25 MHz74HC574 LatchesAD9831 (48-Pin TQFP)0.1 µF Ceramic Chip Capacitor10 nF Ceramic Capacitor0.1 µF Ceramic Capacitor10 µF Tantalum Capacitor10 kΩ Resistor50 Ω Resistor3.9 kΩ Resistor300 Ω ResistorLinksLK1–LK4LK5SwitchSWSocketsMCLK, PSEL0,PSEL1, FSELECT,IOUT, REFINConnectorsJ1J2, J3Three Pin LinkTwo Pin LinkEnd Stackable Switch (SDCDouble Throw)Sub-Miniature BNC Connector36-Pin Edge ConnectorPCB Mounting Terminal Block–14–
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元器件交易网www.cecb2b.com
AD9831
OUTLINE DIMENSIONSDimensions shown in inches and (mm).Thin Quad Flatpack (TQFP)ST-480.063 (1.60) MAX0.030 (0.75)0.018 (0.45) 0.354 (9.00) BSC0.276 (7.0) BSC0.030 (0.75)0.057 (1.45)0.018 (0.45)0.053 (1.35)SEATINGPLANE0.006 (0.15)0.002 (0.05)0° MIN0° – 7°0.007 (0.18)0.004 (0.09)4837136CCSSBB )TOP VIEW)00.0(PINS DOWN)7.(9 (6 7425.30. 0 122513240.019 (0.5)0.011 (0.27)BSC0.006 (0.17)–15–
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