写出4位串入、串出移位寄存器的verilog HDL描述(要...
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发布时间：2022-04-20 22:21
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时间：2024-10-25 15:06
1. shift reg
module shift_4(clk,rst,in,out)
input clk,rst;
input in;
output out;
wire out;
reg [3:0] shiftreg;
always@(posedge clk or negedge rst) // 异步清零
if(!rst)
shiftreg<=0;
else begin
shiftreg[0]<=in;
shiftreg[1]<=shiftreg[0];
shiftreg[2]<=shiftreg[1];
shiftreg[3]<=shiftreg[2];
end
assign out=shiftreg[3];
endmodule
2.ALU
`define ADD 2'h0
`define SUB 2'h1
`define AND 2'h2
`define OR 2'h3
module ALU(a,b,f,s)
parameter N=16;
input [N-1:0] a,b;
input [1:0] f;
output [N-1:0] s;
reg [N-1:0] s;
always@(a or b or f)
case(f)
`ADD: s<=a+b;
`SUB: s<=a-b;
`AND: s<=a & b;
`OR: s<=a | b;
default: s<=s;
endcase
endmodule
